Low dimensional carbon nanostructures, especially graphene, have attracted significant interest due to promising applications ranging from high-speed electronics to sensing. Preparation of graphene layers by thermal decomposition of SiC has been studied as a promising method for the synthesis of homogeneous, wafer-size graphene layers for technological applications. The growth of graphene on bulk hexagonal polytypes of SiC has been extensively studied and we have presented a model for the evolution of the graphene in this process. The growth of graphene on epitaxial 3C-SiC/Si substrates is an appealing alternative to the growth on bulk SiC for cost reduction and for integration with Si based electronic devices.
Here, we present a study of the synthesis of graphene on 3C SiC/Si substrates via high temperature annealing in a vacuum furnace. The quality and number of graphene layers have been investigated using RAMAN Spectroscopy and Transmission Electron Microscopy (TEM). The Ex-situ measurements confirm the dependence of the number of graphene layers on the annealing temperature as well as an improvement via a low temperature anneal of the epitaxial SiC.
Air Force Research Laboratory, Materials and Manufacturing Directorate, AFRL/RXPS, Wright Patterson AFB, OH 45433, USA